• Released 2015, April
  140g, 10.9mm thickness
  Android 5.0.1
  8GB storage, microSDHC
• 0.1%3,602,435 hits
• 4.5'
  480x854 pixels
• 8MP
• 1GB RAM
  Snapdragon 410
• 1900mAh

Also known as LG Leon 4G LTE H340N; LG Leon Dual SIM with dual-SIM card slots

Network	Technology	GSM / HSPA / LTE
	2G bands	GSM 850 / 900 / 1800 / 1900 - SIM 1 & SIM 2 (dual-SIM model only)
	3G bands	HSDPA 900 / 1900 / 2100 - H340N
	HSDPA 850 / 1700(AWS) / 1900 - T-Mobile
	4G bands	1, 3, 7, 8, 20 - H340N
	2, 4, 12 - T-Mobile
	Speed	HSPA 21.1/5.76 Mbps, LTE Cat4 150/50 Mbps

Launch	Announced	2015, February
	Status	Available. Released 2015, April

Body	Dimensions	129.9 x 64.9 x 10.9 mm (5.11 x 2.56 x 0.43 in)
	Weight	140 g (4.94 oz)
	SIM	Single SIM (Micro-SIM) or Dual SIM (Micro-SIM, dual stand-by)

Display	Type	IPS LCD
	Size	4.5 inches, 55.8 cm2 (~66.2% screen-to-body ratio)
	Resolution	480 x 854 pixels, 16:9 ratio (~218 ppi density)

Platform	OS	Android 5.0.1 (Lollipop)
	Chipset	Qualcomm MSM8916 Snapdragon 410 (28 nm)
	CPU	Quad-core 1.2 GHz Cortex-A53
	GPU	Adreno 306

Memory	Card slot	microSDHC (dedicated slot)
	Internal	8GB 1GB RAM
	eMMC 4.5

Main Camera	Single	5 MP or 8 MP, AF
	Features	LED flash
	Video	1080p@30fps

Leon Slotin

The slot also has wild symbol to improve your odds of winning. The Lion symbol in the game, as you may have expected, is the wild symbol. While it appears randomly on single slots during a normal spin, it turns into a stacked wild during the free spins feature, further bettering your chance to win. IGN has the stats and details for every Resident Evil 2 Weapon in our Wiki Guide. In both Leon and Claire's playthroughs, you can find a variety of different Weapons found in all sorts of places.

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Selfie camera	Single	VGA
	Video

Sound	Loudspeaker	Yes
	3.5mm jack	Yes

Comms	WLAN	Wi-Fi 802.11 b/g/n, hotspot
	Bluetooth	4.1, A2DP, LE
	GPS	Yes, with A-GPS, GLONASS
	NFC	No
	Radio	FM radio, RDS
	USB	microUSB 2.0

Features	Sensors	Accelerometer, proximity, compass

Leon Slotin Savannah Ga

Battery	Type	Li-Ion 1900 mAh, removable
	Stand-by	Up to 465 h (2G) / Up to 505 h (3G)

Misc	Colors	Titan, Gold
	Models	H324, H340n, H320, LGMS345, H340, H345
	SAR	1.05 W/kg (head) 0.80 W/kg (body)
	SAR EU	0.99 W/kg (head) 0.78 W/kg (body)
	Price	About 120 EUR

Disclaimer. We can not guarantee that the information on this page is 100% correct. Read more

LG Leon - user opinions and reviews

• qiD

damn, this was my first phone lol. please dont leave lg

• ll
• smH

of course the battery works fine ,if it's just a back up phone

• Anonymous
• 0TL

Its working after 5 years without problem.

The LEON2 processor has the following features:

• SPARC V8 compliant integer unit with 5-stage pipeline
  
• Hardware multiply, divide and MAC units
  
• Interface to the Meiko FPU and custom co-processors
  
• Separate instruction and data cache (Hardvard architecture)
  
• Set-associative caches: 1 - 4 sets, 1 - 64 kbytes/set. Random, LRR or LRU replacement
  
• Data cache snooping
  
• AMBA-2.0 AHB and APB on-chip buses
  
• 8/16/32-bits memory controller for external PROM and SRAM
  
• 32-bits PC133 SDRAM controller
  
• On-chip peripherals such as uarts, timers, interrupt controller and 16-bit I/O port
  
• Advanced on-chip debug support unit and trace buffer
  
• Power-down mode
  

The XST version of the processor adds the following features:

• On-chip 0-waitstate scratch pad data RAM
  
• Interface to high-performance IEEE-754 FPU (GRFPU/GRFPC)
  
• Low complexity 32-bit PCI target-only interface
  
• 10/100 Ethernet MAC (based on the Opencores MAC core)
  
• SPARC V8 Reference Memory management unit (SRMMU)
  
• Also synthesizable with Xilinx XST synthesis tool
  
• lncludes synthesis and P&R scripts for several fpga boards
• Supports Cadence NCSIM and GNU GHDL simulators
  

The processor is extensively configurable and can be efficiently implemented on both FPGAs and ASIC technologies. The only technology-specific mega-cells needed are ram cells for caches and register file.
Simulation
The model comes with a generic testbench and test program, and includes support files for the Synopsys VSS and Modelsim simulators. It also features a built-in disassembler for debug purposes. Below is a screen-shot of LEON being simulated in modelsim. (click on image for full view).

Synthesis
The VHDL model is fully synthesisable and contains synthesis scripts for Synopsys FPGA-Compiler, Synopsys-DC, Synplify and Xilinx XST (-xst version of leon only). Targeting a 0.25 um CMOS process (std-cell), more than 125 MHz can be reached with a gate count of less than 30 Kgates. The processor also fits in an Altera 10K200E FPGA or Xilinx XCV300. Synthesis is straight-forward thanks to the robust design style: fully synchronous, single clock, no false paths, all inputs and outputs are latched. A paper describing the coding style used in LEON can be found here.

The following synthesis results have been achieved:

Technology	Area	Timing
Atmel 0.18 CMOS std-cell	35K gates + RAM	165 MHz (pre-layout)
Atmel 0.25 CMOS std-cell	33K gates + RAM	140 MHz (pre-layout, log file)
UMC 0.25 CMOS std-cell	35K gates + RAM	130 MHz (pre-layout)
Atmel 0.35 CMOS std-cell	2 mm2 + RAM	65 MHz (pre-layout, log file)
Xilinx XC2V3000-6	5,000 LUT + block RAM	80 MHz (post-layout, log1, log2)
Altera 20K200C-7	5,700 LCELLs + EAB RAM	49 MHz (post-layout) log file
Actel AX1000-3	7,600 cells + RAM	48 MHz (post-layout) log file

The area in the table reflects the complete processor with on-chip peripherals and memory controller. The area of the processor core only (IU + cache controllers) is about half of that. The timing for the ASIC technologies has been obtained using worst-case process corner and industrial temperature range.
Configuration
The VHDL model can now be configured using a graphical tool built on tkconfig from the linux kernel. This allows new users to quickly define a suitable custom configuration. Below is a snapshot of the tool under linux (click on image for larger view):
SPARC V8 compliance
The LEON2 processor has been formally certified by SPARC international as being SPARC V8 compliant. The certification was achived on April 2, 2003, and was co-sponsored by ESA and Silicon and Software Systems.
Embedded software
Being SPARC V8 compliant, compilers and kernels for SPARC V8 can be used with LEON (kernels will need a LEON bsp). To simplify initial software development, Gaisler Research is providing LECCS, a free C/C++ cross-compiler system based on gcc and theRTEMS real-time kernel. LECCS allows cross-compilation of single or multi-treaded C and C++ applications for both LEON and ERC32. Using the gdb debugger, it is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware. Gaisler Research also provides TSIM, a high-performance LEON simulator which seamlessly can be attached to gdb and emulate a LEON system at more than 10 MIPS.

A LEON (and ERC32) port to the eCos real-time kernel has been made, and is included in the current eCos v2.0 CVS repository. The binaries are compatible with TSIM, mkprom, rdbmon and DSUMON. No support for a hardware FPU is currently provided, but emulated FP operations using -msoft-float works fine. The LEON target package is called leon, you should thus use ecosconfig new leon to create a leon configuration. For further information on eCos, see the eCos documentation page.

Those interested in JAVA on LEON can take a look at the UCLA Thumbod project. Thumbpod is based on LEON and uses KVM from Sun to execute the java-based application software.

LINUX support for LEON is provided through a special version of the SnapGear Embedded Linux distribution. SnapGear Linux is a full source package, containing kernel, libraries and application code for rapid development of embedded Linux systems. The LEON port of SnapGear supports both MMU and non-MMU LEON configurations, as well as the optional V8 mul/div instructions and floating-point unit (FPU). A single cross-compilation tool-chain is provided which is capable of compiling the kernel and applications for any configuration.
On-chip Debug support unit
The advanced Debug Support Unit (DSU) in LEON2 allows non-intrusive debugging and tracing of applications running on LEON target hardware. The DSU can insert both breakpoints and data watchpoints, and provides full access to all on-chip registers and buses. A trace buffer makes it possible to trace executed instructions, AHB bus transfers, or both. The DSU communicates with an outside monitor through a dedicated uart, and does not need any (expensive) special hardware. Gaisler Research provides the multi-platform monitor GRMON that supports both stand-alone debugging as well as an interface to the GDB debugger.

Performance
Using the Dhrystone 2.1 benchmark, LEON executes around 1,500 dhrystones/s/MHz. This translates to roughly 0.85 dhrystone MIPS/MHz. Configurations with hardware mul/div and larger caches usually performs somewhat better. The dhrystone benchmark was compiled with LECCS-1.1.5 (gcc-2.95.3) using -O2 optimisation.
Sample LEON implementations
Below are a few LEON ASIC implementations made by various companies and research institutions. Click on the links for further details.

LEON2-based NJ1030 GPS baseband receiver by Nemerix (CH)

A rad-hard LEON2-FT implementation is being developed by Atmel under ESA contract.

A family of LEON2 based devices for consumer and military applications is availble from Orbita.

NEW: a list of research projects using LEON is available here.
LEON Development boards
Gaisler Research and Pender Electronic Design have developed a low-cost FPGA prototyping board suitable for LEON development. The board includes a Virtex-II XC2V3000 FPGA, 8 Mbyte flash prom, 1 Mbyte SRAM and 64 Mbyte PC133 SDRAM. The board has a PCI form factor and can be used stand-alone as well as inserted in a legacy PC. Two 120-pin connectors are provided for custom expansion. Boards with larger FPGAs as well as LEON ASIC implementations are also available. For more information, see the boards page.
Download

The LEON VHDL model is provided under the GNU LGPL license. To download, proceed to the download page.
Email lists
Two email lists are available for those interested in the LEON development and utilisation.

• leon_sparc is a general list discussing all aspects of leon utilisation, synthesis and software development.
• leon_announce is a read-only list announcing new leon releases or bug fixes.

LEON in the press

• EETimes: Momentum builds for open-source processor
• EETimes: European Space Agency launches a free SPARC-like core

Links to other LEON sites and projects

• Comparison of LEON2, Microblaze and Openrisc processors
  
• LEON on Cyclone FPGA + comparison with Nios processor
  
• Atmel Rad-Hard LEON2-FT
  
• The UCLA Thumbpod project (Xilinx Xcell article)
  
• LEON2 IEEE802.11a system by A-Star
  
• Ogg Vorbis hardware audio decoder. Has a useful report on how to use LEON in SOC designs.
• Ogg Vorbis audio encoder. Mixes LEON VHDL code with Handel C.
• Orbita LEON2 embedded controllers
  
• Embedded Systems. A project to evaluate various processor cores, including LEON.
  
• ChipSat LEON-based spacecraft controller.
• 16-bit SDRAM controller for LEON

* SPARC is a registered trademark of SPARC International.